1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, more particularly, to a method of forming a trench isolation which improves characteristics of trench filling layer.
2. Description of Related Art
With the recent trend toward high density devices, the art of isolating devices built on a semiconductor substrate becomes one of most important aspects of the integrated circuit industry. Improper device isolation may cause current leakages, which can consume significant power for the entire chip. In addition, improper device isolation can further escalate latch-up, resulting in momentary or permanent damage to the circuit function. Still further, improper device isolation can result in noise margin degradation, voltage shift and/or crosstalk.
The conventional LOCOS(local oxidation of silicon) process is used to develop regions which laterally isolate the active device regions on the integrated circuits. As well known in the art, the structure mentioned above possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird's beak, and the lateral diffusion of channel-stop dopants, making the dopants encroach into the active device regions, making the physical channel width less than the desired channel width. The reduced portion overtaken by both effects will make the situation even worse when devices are scaled down for very large scale integration(VLSI) implementation, increasing threshold voltage and reducing the current driving capability.
According to the disadvantage mentioned above for the LOCOS isolation structure, an isolation technique using shallow trench has been developed. Generally, the shallow trench isolation(hereinafter referred to "STI") includes etching a silicon substrate to a predetermined depth thereby to form a trench, depositing CVD (chemical vapor deposition) oxide layer to fill up the trench, and planarizing the CVD oxide layer.
However, the STI technique also possesses some inherent drawbacks resulting from the processes, i.e., substrate defects during plasma etching the semiconductor substrate, result in dislocation, thereby increasing junction leakage, constant turn on phenomenon of the source and drain of the transistor.
FIG. 1 is a schematic view showing annealing recipe for densification of the trench fill layer according to a prior art method. Referring to FIG. 1, annealing for densification of the trench fill layer includes a stand-by state at a temperature between 400.degree. C. and 650.degree. C., a ramp up stage 2 for increasing the temperature from the stand-up state value to 1000.degree. C. at a rate of 7.5.degree. C./min, an annealing stage 4 for densification of the trench fill layer at 1000.degree. C., a ramp down stage 6 for decreasing temperature from 1000.degree. C. back down to the 400.degree. C. to 650.degree. C. of the stand-by state at a rate of 3.3.degree. C./min, stand-by states 3 and 5 before and after the annealing stage 4, respectively, and an unloading stage 7 of substrate.
However, the substrate point defects resulting from etching the semiconductor substrate can grow along in a specific direction thereby forming a dislocation plane or a dislocation line while going through the annealing for densification of the trench fill layer. The dislocation plane or line usually occurs in the edge or sidewall of the trench and serves as a leakage source. This is due to the strong stress caused by the difference between the thermal expansion coefficient of the semiconductor substrate and that of the trench fill layer.